Verilog 101 - get start

reference : http://design-ark.blogspot.tw/2012/12/hello-verilog.html
reference : http://iverilog.wikia.com/wiki/Getting_Started

[1] The simplest code for Verilog, please save it as hello.v 

code :

module main;
initial
    begin
      $display("Hello, World");
      $finish ; /* optional */
    end
endmodule

ps : 

module, endmodule -> declaration

main -> module name

$display -> just like printf in C

[2] compiler : Icarus Verilog

- Please download from  : http://bleyer.org/icarus/
-  setup the environment path

[3]  compile & execution (in case you use Windows and work in C:\ directory)

-  c:\iverilog -o hello hello.v
-   c:\vvp hello